Contemporary data processing and communication systems, as well as consumer systems, contain one or more CPUs (central processing units), main or system memory (volatile and nonvolatile), and various peripheral devices such as chip sets and hard disks for mass storage. The CPU is typically in one VLSI (very large-scale integrated circuit). The main or system memory, any dedicated memory such as graphics memory, the hard disks, and the controller circuitry associated with them comprise the memory subsystem. The ultrafast, relatively small cache memories (generally called L1, L2, possibly L3) built into the CPU are also usually considered part of the memory subsystem. Main or system memory typically consists of module(s) made up of DRAMs, SRAMs, and nonvolatile memory like flash. A module contains many such memory devices. Each of the DRAM (or SRAM, or flash) devices is organized into a number of subunits, called banks, blocks, sectors, subarrays etc. Each subunit contains a row×column matrix or matrices, with a storage cell or cells at each intersection of row and column. In order to access a bit, byte, several bytes, a word, a page, or other unit of data in the memory subsystem, an address (eventually decoded) consisting of a device address, bank address, row address, column address, and any other predetermined sequences of data (called bursts) must be provided. All memory subsystems operate through LOADs (or READs) from the memory subsystem, and STOREs (or WRITEs) to the memory subsystem by the CPU.
The controller devices and circuitry that interface between the CPU and the memory subsystem make up the system's memory management unit (MMU). The MMU, which may be in part physically integrated into the CPU and/or located in chip sets associated with the CPU, typically includes among other devices an Address Translation Table (ATT). The ATT receives and operates on all requests from the CPU for LOADs and STOREs to and from the memory subsystem. All units of data transmitted in this process contain the actual or content data, along with the address information indicating where, as viewed from the CPU, the content data is (for a LOAD) or will be (for a STORE) located in the physical memory. But, for more efficient manageability of data in available physical locations within the total memory space, those locations being in some degree non-contiguous, fragmented, or random, the addresses specified by the CPU (often called “logical” or “virtual” addresses) are translated or mapped by the ATT into the physical addresses. Such address translation or mapping causes the physical addresses to be presented to the operating system and CPU as contiguous, unfragmented and optimally structured addresses for best system performance. The ATT that performs this function could be in software, either as a part of the operating system, or as a part of a separate translation utility, or as a part of an application programming interface (API). The ATTs can also be implemented in hardware in the CPU, or an associated chip set, or a memory controller that interfaces the CPU with the MMU and the memory subsystem. Some CPUs have the memory controllers as a physically integral part of the CPU itself, though the controllers are functionally part of the MMU. Additionally, modern operating systems allow each program to create its own virtual protected memory space, for faster look-up of relevant addresses, which results in more efficient data access, consisting of LOADs and STOREs as noted. In this scheme, the address “tags” and/or “pointers” that correlate the logical address blocks with actual locations in physical memory are usually cached in Translation Look Aside Buffers (TLBs) which are an integral physical part of the CPU (or sometimes, its associated chip set) and also functionally comprise a component of the MMU.
For content data access to or from the memory subsystem, the physical addresses have to be decoded on the associated chip set level using the ATT and/or the cached address tags (pointers) from the TLBs. The chip sets typically have the MMU's memory controllers as an integral part—the memory controllers perform command, control, clock, address, and any other necessary service functions (e.g., DRAM refresh). In nonvolatile memory controllers (flash controllers), a refresh function is not necessary. However, “write verify” functions, or, “erase before program” functions and associated steps are executed by such a memory controller. If ferroelectric memories are the devices in a memory subsystem, the memory controller may have a different set of functions to be served. Physical addressing to the devices can be either multiplexed addressing or non-multiplexed addressing (divided in time domain, and, triggered by a system clock).
In today's electronic machines, when the CPU needs access to the memory subsystem for the purpose of executing a READ or WRITE operation on data, it generates a logical address as described earlier. This logical address in turn is translated by the address translation table to an address in physical memory as described earlier and the pointers are stored in the TLBs. This is the dominant process used to convert logical addresses to physical addresses and to keep track of the entries. The memory controller may optimize the physical memory depending on available storage locations, and any other application-dependent requirements for contiguous memory. Let us consider a representative example of a DIMM (DRAM Dual-in-line Memory Module), Micron Technology Inc.'s MT36VDDF256722—GB DIMM. DRAM DIMMs are used as system memory in PCs and servers. This device has 134,217,728 (=227) addressable locations in physical memory. Thus the CPU/memory controller needs to control 27 total address bits (13 row and 12 column bits, plus 2 bank select bits). These 27 address bits are the same for any memory access, namely, READ or WRITE etc. Hence, if an intruder accesses data (performs a READ), subsequently manipulates/corrupts the data, and that altered data is written back to the same location in physical memory from which it was (first) accessed, data tampering or trashing occurs. No reasonable amount of data scrambling or encryption can mitigate the above event, nor can the correct data be recovered. Alternatively, an intruder can employ a sequence of READs for the purpose of stealing random blocks of data rather than tampering with or trashing it. Because this type of transaction is extremely fast, large databases can be copied with the expectation that they will contain data (content, information) useful for the intruder.
Under the current art, for a malicious intrusion over a network such as the Internet, intranet, VPN, LAN (wired and wireless) or the like to succeed, the intruder need only gain access to the targeted computer or other device (server, workstation, hard disk, smart card) so as to be able to issue instructions to the device's memory subsystem. All content data including that targeted by the intruder must pass through the memory subsystem, for any access (LOAD or STORE, READ or WRITE). Access could occur through the targeted machine's network connection which involves the CPU (or chip set, or a base station) or similar devices. DMA (Direct Memory Access) is also possible, bypassing the CPU (or similar functional device). In a machine with dedicated graphics memory, an intrusion could also occur through the graphics memory controller. In a smart card type portable system, the memory subsystem could comprise flash memory or ferroelectric memory or phase-change memory or plastic memory or molecular memory or carbon nanotube memory, or a combination of any of the above in a chip stack with either DRAM or SRAM. In conventional systems not employing the invention described herein, once the intruder has succeeded in breaching the external defense such as a firewall, the intruder will be able to retrieve data and issue new instructions to the memory subsystem.
With respect to firewalls in conventional current practice, “firewall” is a broadly used term including a variety of hardware and/or software arrangements that enforce a network owner's policies governing access to and from systems on a network. Suffice it to say, today's firewalls are data-centric and data-driven, in that they consist primarily of data encryption and decryption algorithms plus user authentication procedures. However, data encryption and decryption dramatically increases memory overhead, and slows down system performance, in addition to hogging precious bandwidth. Even if layers of data encryption (or data scrambling) are employed, decryption technology keeps pace with it very quickly. Log-in names, passwords, and similar or more sophisticated user authentication procedures for logins are some of the mechanisms used in the industry today for verifying access permissions. In addition, inside-the-firewall defensive measures are widely used. These include frequent updating of virus detection and elimination software to combat malicious data theft, trashing, denial-of-service attacks, Trojan horses, worms, and the like. However, even with implementation of all these known measures, the electronics industry has not been able to prevent these attacks. Hence, a need has arisen to take content security to a new level, at minimal cost, without undue sacrifice of performance (e.g., increased latencies and reduced bandwidth).